Incorporating VHDL programming and implementation using programmable logic devices (PLD) in fundamental digital design course for Electronics Engineering at undergraduate level has become increasingly essential. However it is experienced that integration of VHDL with fundamentals of digital design in one course students give lesser time and importance for VHDL programming. Hence learning objective related to VHDL programming is not achieved up to the expected level. Experience of giving additional training to interested students had shown improvement in students' performance. This paper discusses effect of designing of a separate compulsory laboratory course in VHDL and its effect on the understanding of students and achieving the learning objectives. It also discusses the effect on performance of students in Digital Design course after separating VHDL programming from it. The feedback of students shows that students learn better in laboratory course and they are motivated to learn further in the same area.